In-network compute and fine-grained NVLink overlap redefine GPU cluster architecture
Collective operations (all-reduce, all-gather) moving into the network fabric frees GPU SMs for compute. Asynchronous bulk device-initiated networking and tile-granularity overlap (KB not MB) require new programming models. NVL72's 72-GPU domain and future scale-up make networking the primary architectural lever for cluster efficiency.
Copper-to-optical conversion inside AI racks to drive 100x volume surge
Physics limits of copper at higher speeds force hyperscalers to replace Ethernet cables with optical interconnects at the rack level (scale-up), expanding the optical market from thousands to hundreds of millions of units per quarter.
Starlink subscribers doubled YoY to 12M (1.7M added in quarter alone), pure exponential curve. Direct-to-cell partnership with carriers + spectrum acquisition strategy aims to eliminate dead zones globally. Gwynne Shotwell claims foundational competitive advantage vs Verizon/AT&T. Hosts expect iPhone integration within 12 months.
Multi-data-center distributed training emerges as key architecture for >1 GW clusters
Google's Omaha and Columbus sites demonstrate production-scale multi-campus training connected by massive fiber interconnects, enabling single logical clusters beyond single-site power and construction constraints — a pattern other hyperscalers are adopting.
Photonic networking emerges as critical enabler for heterogeneous chip clusters
Light-based chip interconnects (photonics) unlock new system architectures for heterogeneous compute but require co-design with compute chips. This networking layer is a ripe innovation area where individual companies need testbeds (like ARIA's scaling inference lab) to demonstrate value with real compute workloads, accelerating the cost curve.
New internet protocol needed for AI-to-AI and AI-to-human communication
Current internet protocols and operating systems are designed for humans; a new protocol stack is needed for efficient AI-to-AI and AI-to-human interaction at scale.
Co-packaged optics entering production with 5x power savings and 10x reliability gains
NVIDIA's co-packaged optics (CPO) for Spectrum-X switches moves into production in H2 2025, integrating optical engines directly with switch ASICs to cut optical networking power by ~5x and improve mean time between interrupts by 10x, addressing the critical power bottleneck where optics consume ~10% of AI factory compute capacity.
NVIDIA becomes largest networking company via NVLink 72 and Spectrum-X CPO; NVLink chip-to-chip scales CPUs
NVLink 72 and NVLink switches created for Grace Blackwell made NVIDIA the largest networking company; Spectrum-X introduces 200Gbps co-packaged optics; NVLink-C2C now connects GPUs directly to CPU fabric and scales Vera CPUs multi-socket — networking is the backbone of disaggregated agentic computing.
Ethernet displacing InfiniBand in AI backend networks as standards win
Arista is bringing cloud-proven Ethernet/IP standards into AI backend networks, replacing fragmented proprietary protocols (InfiniBand, PCI, CXP) with a unified standards-based fabric that scales to hundreds of thousands of accelerators.
Co-packaged optics (Spectrum CPO) eliminates PCB signal degradation, saving tens of megawatts per AI factory
Running electrical signals across PCBs to front-panel optics degrades signal integrity; placing optics directly next to the ASIC inside the package preserves signal quality and cuts power dramatically, freeing megawatts for additional GPU compute.
6G will be enterprise-oriented with AI-driven dynamic network tuning and embedded security
6G shifts from consumer video to enterprise AI workloads requiring low latency, high device density, and native security; AI already dynamically steers cell sites to follow demand (e.g., marathons), improving efficiency.
Chip-to-chip optics at 1.8 TB/s create new semiconductor bottleneck
Blackwell's all-to-all rack connectivity at terabyte-per-second speeds pushes electrical signaling to physics limits, making co-packaged optics and optical circuit switching the next critical innovation frontier for cluster scaling.
Copper's thermal limits at scale make photonics the inevitable medium for GPU-to-GPU communication
As GPU clusters expand to hundreds of thousands of accelerators, the distance and data volume exceed copper's signal integrity and thermal budget; optical fiber transceivers (Lumentum, Corning) offer lower joules-per-bit and speed-of-light latency, creating a multi-year upgrade cycle for the interconnect layer that Jensen Huang is already funding with billions in strategic investments.
Power networking and optical interconnects identified as next AI data-center bottleneck after GPUs and memory
Jensen Huang explicitly named power networking — optical fiber, high-speed interconnects, power management across GPU clusters — as the next constraint. Marvell, as the specialist in this layer, received a $2B Nvidia investment and public endorsement, signaling a multi-year investment cycle for networking silicon and optical components.
Copper interconnect wall forces $4B Nvidia bet on silicon photonics for AI scale-out
Interconnect speeds must quadruple to 1.6Tbps by 2027 as Nvidia scales racks to 576 GPUs; copper hits physics limits (heat, signal degradation, crosstalk) past 800Gbps, making photonics the only viable solution for AI cluster scale-out.
CPO is the biggest unlock for AI data centers over next 5 years
Nvidia, Meta, CoreWeave, and Microsoft all confirm co-packaged optics as the critical shift for scale-out networking; reduces power 4x vs pluggable transceivers, cuts components/lasers 4x, enables higher compute density per watt.
Vertical integration in photonics becomes key differentiator for AI data center connectivity
As data centers shift from copper to fiber for AI traffic, owning the photonic chip stack and fabrication (as Nokia now does via Infinera) captures the same value the market ascribes to pure-play optical vendors like Coherent and Lumentum at 9-25x revenue multiples.