dylan patel

T2 · manager / operator

Founder and chief analyst of SemiAnalysis, an independent research firm covering semiconductors, AI infrastructure and compute economics.

53 calls·26 names·64% bull·last heard 23 days ago·SemiAnalysis+3
track recordleaderboard →
hit rate
80%
avg alpha
+28.2pp
scored
5

top calls

best measured alpha vs SPY · one per company
1st+135.9pp vs SPY
$AMDAdvanced Micro Devices

AMD MI455X with 432GB HBM4 and Helios Rack could make 2026 a turning point against Nvidia if delivered on time

MI455X uses CDNA 5 architecture with 320B transistors across 12 chiplets on 2nm/3nm via 3.5D packaging, delivering 432GB HBM4 at ~20 TB/s bandwidth — a memory advantage over Nvidia's Vera Rubin until Rubin Ultra arrives.

2nd+20.3pp vs SPY
$GOOGLAlphabet

Google's vertical TPU stack gives lowest AI inference COGS

Google's full vertical integration — custom TPUs, proprietary models, and infrastructure — delivers the lowest cost per token, positioning it to capture both consumer and enterprise AI markets as inference costs become critical.

3rd+4.2pp vs SPY
$AMZNAmazon

Amazon Trainium 3 with 144GB HBM3E sees massive deployment; Anthropic and OpenAI adoption validates large-scale ASIC viability

Hundreds of thousands of Trainium 2 already deployed in AWS data centers; Trainium 3 on TSMC N3P with 125B transistors and 144GB HBM3E unifies training/inference, with Anthropic's Claude and OpenAI's 2GW commitment proving hyperscale ASIC traction.

53 total
$QCOM
···
Qualcomm
MEDdylan patel·SemiAnalysis·5 months ago
Qualcomm AI 200 targets inference with LPDDR5X but memory costs rising; AI 250 compute-near-memory could be worthwhile
AI 200 uses 768GB LPDDR5X on TSMC N3E for inference, but LPDDR5X prices are skyrocketing; the successor AI 250 promises 10x effective memory bandwidth with compute-near-memory architecture and LPDDR6, making it a potential future contender.
"But what might matter is the new AI 200 chip Qualcomm announced in October last year. With about 70 billion transistors produced on TSMC's N3E and 768 GB of low-power DDR5X memory…"
1:00
$NVDA
···
Nvidia
HIGHdylan patel·SemiAnalysis·5 months ago
Nvidia Vera Rubin VR200 with 35 petaflops FP4 and NVL72 rack will likely top 2026 charts; Rubin Ultra with 1TB HBM4 to answer AMD memory advantage
VR200 on TSMC N3B with 288GB HBM4 at 22 TB/s delivers 35 petaflops FP4 per package; 72-chip NVL72 rack with NVLink scale-up network makes it the most anticipated 2026 release, with Rubin Ultra's 1TB HBM4 addressing MI455X's memory lead.
"Nvidia is number one for a reason, and with Vera Rubin, Nvidia is taking the next step, moving to TSMC's N3B and HBM4. A single VR200 can crank out an insane 35 petaflops of FP4 p…"
7:11
$AMZN
···
Amazon
HIGHdylan patel·SemiAnalysis·5 months ago
Amazon Trainium 3 with 144GB HBM3E sees massive deployment; Anthropic and OpenAI adoption validates large-scale ASIC viability
Hundreds of thousands of Trainium 2 already deployed in AWS data centers; Trainium 3 on TSMC N3P with 125B transistors and 144GB HBM3E unifies training/inference, with Anthropic's Claude and OpenAI's 2GW commitment proving hyperscale ASIC traction.
"There are hundreds of thousands of Trainium 2 chips deployed inside the AWS AI data centers in Canton and New Carlisle, which makes Trainium 3 a top contender for future large-sca…"
9:24
$META
···
Meta Platforms
MEDdylan patel·SemiAnalysis·5 months ago
Meta MTIA v3 on TSMC N3P with HBM targets recommendation model inference; custom silicon for margins, external GPUs for training
MTIA v3 moves to HBM on TSMC N3P (>100B transistors) for internal inference workloads including Facebook/Instagram recommendation models, delivering margin advantage; Meta uses external Nvidia/AMD/Google chips for training while shifting inference to own silicon, with roadmap expanding.
"The Meta Training and Inference Accelerator, MTIA for short, is now in its third iteration. We don't know all the specs yet, but it will be produced in TSMC's N3P with very likely…"
8:19
$INTC
···
Intel
MEDdylan patel·SemiAnalysis·5 months ago
Intel Jaguar Shores GPU on 18A with 288GB HBM4 competitive on paper but 2027 timeline; must prove manufacturability and software after repeated failures
Jaguar Shores specs (18A, 175B transistors, 288GB HBM4) look competitive for 2027, but Intel's history of failed AI GPU attempts means it must demonstrate both manufacturing execution and software stack maturity; a viable third GPU vendor would be welcome but remains unproven.
"But it doesn't seem like Jaguar Shores is targeting a 2026 release. But with so many ASICs, I had to talk about one more GPU, even if it might be a 2027 product. Jaguar Shores com…"
11:19
$MSFT
···
Microsoft
MEDdylan patel·SemiAnalysis·5 months ago
Microsoft Maia 200 with 216GB HBM3E targets FP8/FP4 inference for in-house and OpenAI models; custom silicon gaining inference share from Nvidia
Maia 200 at 825mm² with 140B transistors on TSMC N3P delivers 5/10 petaflops FP8/FP4 with 216GB HBM3E; Microsoft will use it for internal models and future ChatGPT models, exemplifying the trend of inference moving from Nvidia to hyperscaler custom silicon.
"With Maya 200, we have the answer. At around 825 sq mm, the almost radical-busting chip contains 140 billion transistors, is manufactured in TSMC's N3P, and comes with a pretty la…"
10:29
$GOOGL
···
Alphabet
MEDdylan patel·SemiAnalysis·5 months ago
Google Ironwood TPUv7 with optical circuit switches enables 9,216-chip super pods; external customer adoption key for inference TCO leadership
TPUv7 on TSMC N3E with >100B transistors and 192GB HBM3E uses optical circuit switches to connect up to 9,216 TPUs in super pods, offering a differentiated TCO for inference — if external customers can utilize them as efficiently as Google does internally.
"Ironwood, aka TPUv7, is built on TSMC's N3E with very likely over 100 billion transistors. Of course, two large compute chiplets and comes with 192 GB of HBM3E. It's specifically…"
3:29
$AMD
···
Advanced Micro Devices
HIGHdylan patel·SemiAnalysis·5 months ago
AMD MI455X with 432GB HBM4 and Helios Rack could make 2026 a turning point against Nvidia if delivered on time
MI455X uses CDNA 5 architecture with 320B transistors across 12 chiplets on 2nm/3nm via 3.5D packaging, delivering 432GB HBM4 at ~20 TB/s bandwidth — a memory advantage over Nvidia's Vera Rubin until Rubin Ultra arrives.
"AMD is the second major player in the GPU space, and 2026 could be a turning point. If MI455X and the Helios Rack are on time. MI455X is based on the new CDNA 5 architecture and p…"
2:18
$CBRS
···
Cerebras
LOWdylan patel·SemiAnalysis·5 months ago
Cerebras WSE3's 44GB SRAM and 21 PB/s bandwidth unique but memory capacity falling behind 2026 needs; WSE4 announcement anticipated
WSE3's wafer-scale design with 4T transistors on N4P delivers extraordinary SRAM bandwidth, but 44GB capacity is insufficient for 2026 workloads; the concept remains competitive for ultra-fast serving, with WSE4 potentially addressing capacity limits.
"WSE3, as the name implies, uses an entire silicon wafer to create a massive chip. It contains an unimaginable amount of SRAM. No, not megabytes. I'm talking about 44 GB and a theo…"
4:48
$GROQ
Groq
MEDdylan patel·SemiAnalysis·5 months ago
Nvidia acquired Groq for ~$20B; deterministic LPU architecture eliminates latency but requires massive scale for model size; 2nd gen on Samsung 4nm awaited
Groq's LPU uses deterministic execution with 230MB on-chip SRAM on 14nm to eliminate GPU latency, but limited memory requires connecting many chips; Nvidia's ~$20B acquisition signals strategic value, and a 2nd-gen on Samsung 4nm could expand applicability.
"The Croq language processing unit or LPU for short has relatively unspectacular specs, 55 billion transistors on a 14 nanometer Global Foundries node, and no external memory at al…"
5:51