Founder and CEO of Positron, a chip startup developing inference accelerators using systolic arrays and LPDDR memory; previously shipped FPGA-based Archer product and announced Oracle partnership.
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Positron's next-gen Azimov chip uses commodity LPDDR memory to deliver 2.3TB per chip at 400W — 6-8x the memory capacity of Nvidia's B200 at a quarter of the power — while its systolic array achieves a 1:1 matrix-matrix to matrix-vector ratio versus Nvidia's 32:1, enabling far more efficient inference scaling for trillion-parameter models.
Nvidia's architectural focus on dense matrix-matrix training workloads caused the matrix-vector performance ratio to degrade from 16:1 on Hopper to 32:1 on Blackwell, even as total flops doubled — a structural disadvantage for inference where attention mechanisms are memory-bound matrix-vector operations.