myron

Memory capacity growth is gated by ASML's ability to produce EUV lithography tools, which themselves require specialized suppliers (e.g., ultra-smooth mirrors) with long lead times; this creates a hard physical constraint that cannot be solved by capital alone.

Memory vendors are printing massive profits but cannot respond to demand signals quickly because adding wafer capacity requires building clean rooms, filling them with equipment, and waiting for ASML EUV tools which have their own multi-year supply chain; the HBM crunch will not ease this decade.

Nvidia is redesigning Rubin Ultra to use 8-high HBM4 (192GB) instead of 16-high HBM4E (1TB) because HBM wafer supply cannot keep up with logic wafer capacity; the shift optimizes for bandwidth per dollar as inference workloads prioritize token speed over model capacity.

Broadcom is among the major customers securing HBM supply for its custom AI accelerators, indicating broad-based demand for memory across merchant and custom silicon.

Meta is actively requesting semi-custom accelerator variants (e.g., MI450 with 8-high HBM) to avoid overprovisioning expensive memory capacity it doesn't need, setting a precedent for hyperscaler-specific SKUs across the industry.

Moving to 4-high HBM more than doubles harvestable cubes, shifting the bottleneck from HBM wafers to TSMC leading-edge logic wafers and advanced packaging capacity needed to co-package the additional logic dies.

Google is actively managing HBM allocations for its TPU accelerator program, reflecting the same supply chain pressures facing Nvidia and custom silicon vendors.

AMD is already providing custom memory configurations (8-high vs 12-high HBM on MI450) for hyperscalers like Meta, signaling a broader industry shift toward multiple SKUs per accelerator generation to match workload-specific memory needs.