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▶ 1:00 · Memory & Storage · HBM4 adoption and compute-near-memory architectures redefining AI chip memory hierarchy

now playing · Memory & Storage

Memory & Storagetailwindscore 9/10dylan patel

HBM4 adoption and compute-near-memory architectures redefining AI chip memory hierarchy

Next-gen chips (MI455X, Vera Rubin, Jaguar Shores) standardize on HBM4 with 20+ TB/s bandwidth, while Qualcomm's AI 250 pursues compute-near-memory with LPDDR6 — memory bandwidth and capaci…

Data Center Infrastructuretailwindscore 8/10dylan patel

Rack-scale integration (NVL72, Helios, TPU super pods) becoming the unit of deployment for frontier AI

Nvidia's 72-chip NVL72, AMD's Helios Rack, and Google's 9,216-TPU optical super pods show that competitive AI infrastructure now requires system-level co-design of compute, memory, and inte…

Semiconductorstailwindscore 7/10dylan patel

Advanced packaging (3.5D, chiplets) and leading-edge nodes (2nm, 3nm, 18A) enabling trillion-transistor AI accelerators

AMD's 12-chiplet 3.5D package, Nvidia's Vera Rubin on N3B, and Intel's 18A Jaguar Shores demonstrate that 2026 AI chips require heterogeneous integration of multiple leading-edge logic dies…

AI Hardware & Chip Architecturetailwindscore 8/10dylan patel

Hyperscaler custom silicon accelerating inference shift away from Nvidia GPUs

Meta, Amazon, Microsoft, and Google are deploying proprietary ASICs (MTIA, Trainium, Maia, TPU) for inference workloads, leveraging workload-specific optimization and margin advantages whil…

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▶ 1:00 · Memory & Storage · HBM4 adoption and compute-near-memory architectures redefining AI chip memory hierarchy

now playing · Memory & Storage

Memory & Storagetailwindscore 9/10dylan patel

HBM4 adoption and compute-near-memory architectures redefining AI chip memory hierarchy

Next-gen chips (MI455X, Vera Rubin, Jaguar Shores) standardize on HBM4 with 20+ TB/s bandwidth, while Qualcomm's AI 250 pursues compute-near-memory with LPDDR6 — memory bandwidth and capaci…

Data Center Infrastructuretailwindscore 8/10dylan patel

Rack-scale integration (NVL72, Helios, TPU super pods) becoming the unit of deployment for frontier AI

Nvidia's 72-chip NVL72, AMD's Helios Rack, and Google's 9,216-TPU optical super pods show that competitive AI infrastructure now requires system-level co-design of compute, memory, and inte…

Semiconductorstailwindscore 7/10dylan patel

Advanced packaging (3.5D, chiplets) and leading-edge nodes (2nm, 3nm, 18A) enabling trillion-transistor AI accelerators

AMD's 12-chiplet 3.5D package, Nvidia's Vera Rubin on N3B, and Intel's 18A Jaguar Shores demonstrate that 2026 AI chips require heterogeneous integration of multiple leading-edge logic dies…

AI Hardware & Chip Architecturetailwindscore 8/10dylan patel

Hyperscaler custom silicon accelerating inference shift away from Nvidia GPUs

Meta, Amazon, Microsoft, and Google are deploying proprietary ASICs (MTIA, Trainium, Maia, TPU) for inference workloads, leveraging workload-specific optimization and margin advantages whil…