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rohan anil

T2 · manager / operator

One of four pre-training leads for Google's Gemini; worked on fundamental AI research at Google Brain and Anthropic; developed the Shampoo optimizer and N-gram memory architectures; focuses on training algorithm optimization and hardware-software co-design.

3 calls·3 names·67% bull·last heard 2 months ago·Sequoia Capital
track record

no scored calls yet — needs a stated position or a categorical verdict, with a matured window vs SPY

top calls

highest conviction · one per company
1sthigh conviction
$CORE-AUTOMATIONCore Automationposition

Core Automation founders bet on test-time learning architectures to replace transformers

Transformers fundamentally cannot learn continuously at test time; new architectures enabling continual learning on real-world distributions are needed, and Core Automation is building an automated lab to discover them.

Sequoia Capital2026-07episode →
2ndmedium conviction
$GOOGLAlphabet

Anil: Google's scale mindset drives inference efficiency focus

Google's requirement to serve billions of users creates unique pressure for latency-constrained, token-efficient architectures that most labs ignore.

Sequoia Capital2026-07episode →
3rdmedium conviction
$DEEPSEEKDeepSeek

Anil: DeepSeek validated N-gram memory replacing MoE

DeepSeek's N-gram embeddings demonstrated improved memory scaling without mixture-of-experts, validating Core Automation's architectural direction.

Sequoia Capital2026-07episode →

most discussed · click a bar to filter

  • $GOOGL
  • $DEEPSEEK
  • $CORE-AUTOMATION

recurring themes

  • AI Infrastructure2
  • AI Hardware & Chip Architecture2
  • AI Economics & Business Models1
3 total
$GOOGL
···
Alphabet
MEDrohan anil·Sequoia Capital·2 months ago·Building the Automated AGI Lab: Core Automation's Jerry Tworek and Rohan Anil
Anil: Google's scale mindset drives inference efficiency focus
Google's requirement to serve billions of users creates unique pressure for latency-constrained, token-efficient architectures that most labs ignore.
"I come from the Google mindset where we had to like serve billions of people. So like finding more efficient architectures that fit have a like a deadline on latency and the numbe…"
18:50
$DEEPSEEK
DeepSeek
MEDrohan anil·Sequoia Capital·2 months ago·Building the Automated AGI Lab: Core Automation's Jerry Tworek and Rohan Anil
Anil: DeepSeek validated N-gram memory replacing MoE
DeepSeek's N-gram embeddings demonstrated improved memory scaling without mixture-of-experts, validating Core Automation's architectural direction.
"Deep Seek wrote uh their N-gram, which is a improved version of adding more memory. Short scaling loss that yeah, you don't need MOEs. You could actually replace it with these N-g…"
43:55
$CORE-AUTOMATION
Core Automation
HIGHrohan anil·Sequoia Capital·2 months ago·Building the Automated AGI Lab: Core Automation's Jerry Tworek and Rohan Anil· position
Core Automation founders bet on test-time learning architectures to replace transformers
Transformers fundamentally cannot learn continuously at test time; new architectures enabling continual learning on real-world distributions are needed, and Core Automation is building an automated lab to discover them.
"Kernel automation is a lab created to build models that continuously learn and then learn from deployment. We believe as I mentioned that transformers are incapable of continual l…"
39:41
8
AI Infrastructuretailwind
Kernel automation is bottleneck for post-transformer architecture search
Writing high-performance kernels (e.g., QR factorization) requires rare human expertise and months of effort; automating this with AI models would unlock orders-of-magnitude faster architecture iteration and enable novel optimizers like Shampoo at scale.
7
AI Economics & Business Modelstailwind
Autoregressive token generation inference inefficiency limits frontier AI accessibility
Current chain-of-thought scaling spends compute one token at a time, making inference costly and limiting frontier model access to a subset of users; architectural changes that increase computational depth without token-by-token generation are needed to expand the addressable market for AI.
7
AI Infrastructuretailwind
End-to-end co-optimization of pre-training and RL unlocks orders-of-magnitude efficiency
Current separate pre-training (perplexity minimization) and RL (chain-of-thought) pipelines are suboptimal; combining them with second-order optimizers like Shampoo and architecture-optimizer co-design can yield 10x+ compute efficiency gains by aligning training objectives with inference-time computation patterns.
7
AI Hardware & Chip Architecturemixed
Biological learning efficiency requires hardware-software co-design beyond digital GPUs
Human brains build custom circuits during development; matching biological efficiency likely needs analog compute with error correction, not just scaling current GPU/TPU architectures.
7
AI Hardware & Chip Architecturetailwind
Kernel generation bottleneck blocks novel architectures; automating it unlocks new algorithmic space
Novel architectures require custom high-performance kernels (e.g., 60x speedup for QR factorization), but current models cannot write them; automating kernel generation via AI-assisted search is the critical inner loop enabling rapid architecture experimentation on modern hardware like B200 GPUs.