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richard ho

T3 · host / generalist

Richard Ho is the Vice President of Hardware at OpenAI, overseeing the design of custom AI chips like Jalapeno.

1 call·1 name·100% bull·last heard last month·Bloomberg Tech
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$OPENAIOpenAIposition

OpenAI's Jalapeno custom inference chip beats Nvidia on throughput/latency, targets 1.8x lower cost per token via Broadcom/TSMC

OpenAI's first custom inference chip (Jalapeno) uses a blank-slate HBM4+SRAM architecture to achieve high throughput and ultra-low latency simultaneously, reducing data movement; developed with Broadcom and TSMC, it aims to lower infrastructure cost per token by ~1.8x as part of a multi-generational roadmap.

Bloomberg Tech2026-08episode →

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  • $OPENAI

recurring themes

  • AI Economics & Business Models1
  • AI Hardware & Chip Architecture1
1 total
$OPENAI
OpenAI
HIGHrichard ho·Bloomberg Tech·last month·Nvidia Earnings, Apple’s AI Macs and OpenAI’s Chip Push | Bloomberg Tech 8/25/2026· position
OpenAI's Jalapeno custom inference chip beats Nvidia on throughput/latency, targets 1.8x lower cost per token via Broadcom/TSMC
OpenAI's first custom inference chip (Jalapeno) uses a blank-slate HBM4+SRAM architecture to achieve high throughput and ultra-low latency simultaneously, reducing data movement; developed with Broadcom and TSMC, it aims to lower infrastructure cost per token by ~1.8x as part of a multi-generational roadmap.
"WHAT WE ARE SEEING WITH JALAPENO'S ARE ABLE TO GET HIGH-THROUGHPUT AND LOW LATENCY WITH THE SAME DEVICE, WHICH IS KIND OF A FIRST IN THE INDUSTRY. ... IT IS AN HBM BASED DESIGN, O…"
24:37
8
AI Economics & Business Modelstailwind
OpenAI's custom inference silicon targets 1.8x lower cost per token, vertical integration to attack full stack
OpenAI's Jalapeno chip aims to cut inference cost per token by ~1.8x via a novel HBM4+SRAM architecture co-designed with Broadcom and TSMC; the multi-generational roadmap reflects a strategy to optimize the entire stack from models to firmware to data centers.
8
AI Hardware & Chip Architecturetailwind
HBM4 and SRAM integration enables breakthrough throughput-latency trade-off for inference ASICs
OpenAI's Jalapeno achieves industry-first simultaneous high throughput and ultra-low latency by integrating HBM4 and SRAM in a blank-slate architecture that minimizes data movement; the design is programmable and already running multiple models months after silicon arrival, validating the software-hardware co-design approach.