mitesh agarwal

Positron's Atlas chip uses LPDDR5X instead of HBM to avoid CoWoS constraints, achieving competitive inference TCO and interactivity; the team shipped FPGA-based Gen1 in 15 months with <20 people, has Gen2 at Oracle, and is taping out Gen3 ASIC for 2027 production targeting gigawatt-scale hyperscaler deployments.

Positron AI uses FPGA-based first-gen and custom silicon second-gen (Atlas racks at Oracle) to run frontier models on commodity LPDDR5X memory, bypassing HBM/CoWoS supply constraints; they aim for hundreds of megawatts by 2028 and gigawatt-scale by 2032 to serve hyperscalers and quant finance, with software stack built on open-source SG Lang/VLLM plus co-optimization with frontier labs.

Video generation models are memory-bound on capacity and bandwidth; solving this with commodity memory architectures (LPDDR5X) enables new silicon entrants to scale without HBM/CoWoS constraints, creating a structural tailwind for memory-centric inference chips.

Positron's chip architecture uses commodity memory instead of HBM to solve the memory bandwidth/capacity bottleneck for inference workloads (video generation, reasoning models), enabling faster supply chain scaling and lower TCO for hyperscalers demanding gigawatt-scale deployments.

Positron's architecture uses commodity LPDDR5X memory instead of HBM to avoid the CoWoS packaging bottleneck that constrains Nvidia, AMD, and TPU supply; this enables faster scaling but requires solving the bandwidth gap through technical innovation, targeting inference workloads where memory capacity and cost matter more than training-scale interconnect.

Frontier labs and hyperscalers now require silicon vendors to show credible paths to hundreds of megawatts by 2028 and gigawatts by 2032, forcing massive upfront capital ($875M raise) and supply-chain locking with TSMC/Blackstone-style project finance.

Video and reasoning models are memory-bandwidth and capacity bound (Google VO needs 4 H100s for 10s clip); Positron's architecture uses commodity LPDDR5X to bypass HBM supply constraints and cost, targeting a TCO advantage for inference workloads while accepting training irrelevance.

Mitesh Agarwal explains that inference is memory-bound on bandwidth and capacity, so Positron uses commodity LPDDR5X instead of HBM to bypass CoWoS packaging constraints, enabling faster scaling to hundreds of megawatts by 2028 without relying on TSMC advanced packaging bottlenecks.