TickerTain
$SPCX····$NVDA····$MSFT····$GOOGL····$ANTHROPIC·$TSLA····$CRWV····$NBIS····$HIMS····$TSM····$ASML····$FIGURE·$LYFT····$UBER····$SNOW····$META····$ELEVENLABS·$CURSOR·$COGNITION·$OPENAI·$AAPL····$RKLB····$XAI·$AMZN····$AMD····$000660.KS····$INTC····
←

doug laughlin

T3 · host / generalist
6 calls·6 names·50% bull·last heard 3 months ago·TBPN
track record

no scored calls yet — needs a stated position or a categorical verdict, with a matured window vs SPY

top calls

highest conviction · one per company
1sthigh conviction
$INTCIntel

SemiAnalysis: Intel foundry stock ahead of technical turnaround; government deal a stroke of genius

Intel 18A process is good enough and customers (Apple, Musk) are committed due to US government top-down mandate, but historical execution risk remains; stock price has outpaced technical reality.

TBPN2026-05→
2ndhigh conviction
$TSMTSMC

SemiAnalysis: TSMC clean room bottleneck drives incremental not revolutionary capacity expansion

TSMC is capacity-constrained by clean room lead times (3-5 years); they expand methodically and incrementally, not revolutionarily, creating persistent shortages that benefit overflow demand for Intel Foundry and other alternatives.

TBPN2026-05→
3rdhigh conviction
$CBRSCerebras

SemiAnalysis: Cerebras IPO succeeds but SRAM scaling wall limits large model inference

Cerebras wafer-scale chips deliver exceptional fast inference for sub-trillion parameter models, but SRAM scaling has stalled (WSE-3 only 10% memory increase over WSE-2), making it unlikely to serve multi-trillion parameter models with large context windows; they captured ~1% of a massive inference market which validates the business but architectural constraints remain.

TBPN2026-05→

most discussed · click a bar to filter

recurring themes

6 total
$GROQ
Groq
MEDdoug laughlin·TBPN·3 months ago
SemiAnalysis: Groq LPU SRAM offload enables disaggregated decode acceleration in GB200 racks
Groq's LPU architecture with extreme SRAM bandwidth fits as a decode accelerator in disaggregated inference pipelines, receiving activations from Nvidia GB200 prefill; moving data off Groq 'island' is easier than Cerebras due to standard interconnects.
"That problem wouldn't work with the Cerebras chip because you're kind of it's an island, right? You think of it as an island of compute. It's really really good at everything in t…"
101:00
$NVDA
···
Nvidia
MEDdoug laughlin·TBPN·3 months ago
SemiAnalysis: Nvidia Blackwell GB200 racks enable disaggregated inference with Groq SRAM offload
Nvidia's GB200 rack architecture allows passing activations to Groq LPU racks for extreme decode speedup, exemplifying the trend toward disaggregated inference where prefill (compute-bound) and decode (memory-bandwidth-bound) are split across specialized silicon; Jensen is excited about this technology tree.
"In the GB200 rack what you can do is you can pass the activations over to the SRAM in the Groq LPU rack and that is an extreme speed up and so it's like that's like a perfect exam…"
100:32
$INTC
···
Intel
HIGHdoug laughlin·TBPN·3 months ago
SemiAnalysis: Intel foundry stock ahead of technical turnaround; government deal a stroke of genius
Intel 18A process is good enough and customers (Apple, Musk) are committed due to US government top-down mandate, but historical execution risk remains; stock price has outpaced technical reality.
"I think it's about execution. Um it's kind of crazy to me that I think the stock price is ahead of the technical turnaround and I think that um I think Lip-Bu Tan clearly has like…"
104:06
$AMD
···
Advanced Micro Devices
MEDdoug laughlin·TBPN·3 months ago
SemiAnalysis: AMD MI300 rack scale-up executing, inference serving demand to follow Nvidia roadmap
AMD is focused on rack-scale execution for MI300/MI350; Lisa Su will figure out inference serving and likely match Nvidia's disaggregated roadmap with a fast SRAM offload FFN chip within 12 months, but candidate technologies are limited.
"AMD is mostly just trying to get the last thing to work, which is the rack scale-up. Um and I think they're going to do a good job of MI350. I think what's going to happen is that…"
102:30
$TSM
···
TSMC
HIGHdoug laughlin·TBPN·3 months ago
SemiAnalysis: TSMC clean room bottleneck drives incremental not revolutionary capacity expansion
TSMC is capacity-constrained by clean room lead times (3-5 years); they expand methodically and incrementally, not revolutionarily, creating persistent shortages that benefit overflow demand for Intel Foundry and other alternatives.
"The shortages specifically at TSMC is driven by clean room. It's a long lead time item. It takes 3 to 5 year or let's just say 3 years to bring a clean room up. And so in order fo…"
108:00
$CBRS
···
Cerebras
HIGHdoug laughlin·TBPN·3 months ago
SemiAnalysis: Cerebras IPO succeeds but SRAM scaling wall limits large model inference
Cerebras wafer-scale chips deliver exceptional fast inference for sub-trillion parameter models, but SRAM scaling has stalled (WSE-3 only 10% memory increase over WSE-2), making it unlikely to serve multi-trillion parameter models with large context windows; they captured ~1% of a massive inference market which validates the business but architectural constraints remain.
"SRAM scaling is dead, meaning that you can't make smaller and smaller SRAM scales. So pretty much they like kind of committed to this dead-end process by having the biggest scale-…"
94:34