TickerTain
TickerTain
NewsroomShortsPortfolioConvergence
NewsroomShortsPortfolioConvergence
←
▶ 22:00 · Memory & Storage · New agentic memory tier (CMX for KV cache, STX for vector/object storage) delivers 5x inference throughput
episode briefing
NVIDIA

COMPUTEX 2026 | NVIDIA Keynote | Extreme Co-Design: Building the AI Factory

2026-07-10 · 1 company · 6 thematic
sentiment
1 bull0 bear0 neu
speakers
kevin deierling

Kevin Deierling leads NVIDIA's networking business and has been with the company for six years since Jensen Huang acquired his previous networking startup. He presented at COMPUTEX 2026 on extreme co-design across the AI factory stack.

now playing · Memory & Storage
AI Infrastructuretailwindscore 9/10kevin deierling
AI factories replace data centers as token revenue generators requiring full-stack co-design
Data centers are being re-architected from cost centers into 'AI factories' that generate tokens as revenue; this requires extreme co-design across energy, chips, infrastructure, models, an…
Grid & Power Infrastructuretailwindscore 8/10kevin deierling
DSX power smoothing enables 40% more GPU density per gigawatt by flattening training power spikes
AI training creates rainfall-like power spikes that stress grid transformers; Nvidia's DSX system stores excess energy during low-demand phases and releases it during peaks, flattening the…
AI Hardware & Chip Architecturetailwindscore 9/10kevin deierling
Seven co-designed chips (Rubin, Vera, NVLink, Spectrum, ConnectX, BlueField, CPO) act as one system to beat copper distance limits
Single-chip design is insufficient; Nvidia co-designs seven chips together with cache-coherent links (NVLink 72), scale-out fabric (Spectrum-6), and co-packaged optics (Spectrum CPO) to ove…
Networking & Optical Infrastructuretailwindscore 8/10kevin deierling
Co-packaged optics (Spectrum CPO) eliminates PCB signal degradation, saving tens of megawatts per AI factory
Running electrical signals across PCBs to front-panel optics degrades signal integrity; placing optics directly next to the ASIC inside the package preserves signal quality and cuts power d…
AI Agentstailwindscore 9/10kevin deierling
Agentic loops create exponential token demand, requiring purpose-built CPU (Vera) and storage architectures
Agents close the prompt loop autonomously, generating 100x more internal tokens per output token; this demands CPUs built for planning/tool use (Vera), accelerated libraries (CUDA-X), and n…
Memory & Storagetailwindscore 8/10kevin deierling
New agentic memory tier (CMX for KV cache, STX for vector/object storage) delivers 5x inference throughput
AI agents require short-term KV cache and long-term vector/object memory distinct from traditional DRAM; Nvidia's CMX/STX reference architecture accelerates prefill/decode and tool use, yie…