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▶ 35:16 · AI Hardware & Chip Architecture · Maximizing compute per communication byte is the universal optimization from gates to data centers

now playing · AI Hardware & Chip Architecture

AI Hardware & Chip Architecturetailwindscore 9/10reiner pope

Systolic arrays beat register-file ALUs by amortizing data movement over quadratic compute

The fundamental constraint in chip design is data movement cost (muxes, register files) scaling linearly with register file size, while compute (multiply-accumulate) scales quadratically wi…

AI Hardware & Chip Architecturetailwindscore 8/10reiner pope

Maximizing compute per communication byte is the universal optimization from gates to data centers

The same compute-vs-communication tradeoff appears at every level: ALU (muxes vs MAC), systolic array (register file vs matrix unit), chip (HBM vs compute), and cluster (interconnect vs GPU…

AI Hardware & Chip Architecturemixedscore 7/10reiner pope

Higher clock speed reduces area efficiency; optimal throughput balances frequency and parallelism

Pipeline registers increase clock frequency but consume area that could be used for compute. Throughput = (compute per cycle) × (cycles per second). Pushing clock too high (e.g., register a…

Semiconductorsheadwindscore 7/10reiner pope

FPGA's 10x area overhead comes from LUT/mux programmability tax; viable only for frequent redesigns

An FPGA lookup table (4-input LUT) implements any 4→1 boolean function using a 16:1 mux costing ~32 gates vs 3 gates for a hardwired 4-input AND. The 10x area/energy penalty is the price of…

Memory & Storagemixedscore 7/10reiner pope

Scratchpads (software-managed) enable deterministic latency; caches (hardware-managed) optimize average throughput

CPUs use caches for general-purpose throughput but introduce non-determinism from cache hits/misses and branch prediction. TPUs and FPGAs use scratchpads — software explicitly manages data…

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