$GOOGL · TPU systolic arrays are the most efficient known circuit for matrix multiply; 128x128 arrays in older generations

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Dwarkesh Patel

Chip design from the bottom up – Reiner Pope

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TPU systolic arrays are the most efficient known circuit for matrix multiply; 128x128 arrays in older generations

2026-05-22 · 3 company · 5 thematic

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speakers

dwarkesh patel

Host of the Dwarkesh Podcast, known for deeply researched long-form conversations on artificial intelligence, science, economics and history.

reiner pope

Reiner Pope is the CEO of MatX, a stealth AI chip startup. He previously worked on TPU architecture at Google. He delivers a blackboard-style lecture on transformer inference economics, covering roofline analysis, batch size optimization, MoE parallelism, scale-up networking, memory hierarchy, and training/inference compute tradeoffs.

quote

“Older TPUs were described as 128x128 of this circuit shown here. This ends up being the most efficient known circuit for implementing a matrix multiply. ... From a very high-level point of view, the GPU has a lot of tiny TPUs tiled across…”

—reiner pope

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